Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important charge storage material for EEPROM devices is a charge trapping dielectric, for example silicon nitride in an oxide-nitride-oxide (ONO) structure. One EEPROM device that utilizes a charge trapping dielectric charge storage layer is a silicon-oxide-nitride-oxide-silicon (SONOS) type flash memory cell. In other such devices, like SONOS, the charge storage is in a charge trapping dielectric layer, but the materials of the various layers may vary from those used in SONOS devices. That is, the silicon, oxide or nitride may be replaced with another material. For example, silicon may be replaced by germanium or silicon-germanium, oxide and/or nitride may be replaced by, e.g., a high-K dielectric material. Such devices, as well as the SONOS device, are generally included within the designation “charge trapping dielectric flash memory” device, as used herein.
In charge trapping dielectric flash memory devices, during programming, electrical charge is transferred from the substrate to the charge trapping dielectric charge storage layer, e.g., the nitride (N) layer in an ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom oxide layer and become trapped in the charge trapping dielectric layer. This jump is known as hot carrier injection (HCI), the hot carriers being electrons. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the charge trapping dielectric layer near the source region. Because the charge trapping dielectric material is not electrically conductive, the charge introduced into the charge trapping dielectric layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous charge trapping dielectric charge storage layer.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a charge trapping dielectric layer and have designed memory circuits that utilize two or more regions of stored charge within the layer. This type of non-volatile memory device is known as a dual-bit or multi-bit EEPROM, or as a charge trapping dielectric flash memory device. Such a device is available under the trademark MIRRORBIT™ from Advanced Micro Devices, Inc., Sunnyvale, Calif. The MIRRORBIT™ device is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left bit and a right bit are stored in physically different areas of the charge trapping dielectric layer, near the left and right regions of each memory cell. The above-described programming methods are used to enable the two bits to be programmed and read independently. The two bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
While the recent advances in charge trapping dielectric flash memory technology have enabled memory designers to double the memory capacity of charge trapping dielectric flash memory arrays using dual-bit data storage, numerous challenges remain in the fabrication of material layers within these devices.
In a charge trapping dielectric flash memory cell, the control gate electrode is separated from the charge trapping dielectric charge storage layer by a top dielectric layer (usually an oxide), and the charge storage layer is separated from the semiconductor substrate (channel region) by a bottom dielectric layer (usually an oxide), forming the oxide-charge trapping dielectric-oxide stack, e.g., the ONO structure. The control gate electrode is isolated from laterally surrounding structures by a gate stack spacer, which conventionally comprises a thin layer (e.g., about 100–300 angstroms) of silicon dioxide and a larger structure of silicon nitride. The conventional gate stack spacer is deposited by PECVD, but this method imparts a significant hydrogen content into the silicon nitride. For example, the conventionally employed PECVD method can impart substantially greater than about two atomic percent, e.g., up to as much as about 30 atomic percent, hydrogen into the silicon nitride of the gate stack spacer. Previously, the hydrogen content in the gate stack spacer has not presented a significant problem to proper functioning of devices such as charge trapping dielectric flash EEPROM memory devices. As noted above, as dimensions continue to be reduced, more variables must be considered in the design and fabrication of semiconductor devices.
Hydrogen content is a variable which may affect performance of semiconductor devices generally, and as exemplified herein, in charge trapping dielectric flash EEPROM memory devices, particularly in view of the continually-sought reduced dimensions of modern semiconductor devices. The present inventors have discovered that hydrogen contained in structures such as the gate stack spacer can migrate into the dielectric layers such as the oxide spacer layer and into the bottom or tunnel oxide layer, and/or into the top oxide layer, and can cause problems such as degradation of device properties. These problems may include adverse effects on the subthreshold slope or transconductance GM after program/erase as a result of the migration. As device dimensions have steadily decreased, the effect of such hydrogen becomes more pronounced, as discovered by the present inventors.
Accordingly, advances in fabrication technology of structures such as the gate stack spacer structure mentioned above are needed to eliminate or reduce problems resulting from hydrogen in the gate stack spacer structure used in charge trapping dielectric flash memory devices. While the present invention is described particularly with respect to a particular embodiment, i.e., the charge trapping dielectric flash memory device, the invention is broadly applicable to any semiconductor device which is susceptible to adverse effects resulting from the presence of hydrogen in dielectric layers.